1. Field of the Invention
The present invention relates to a semiconductor device having a silicon on insulator (hereinbelow referred to as SOI) structure in which a silicon layer is formed on an insulating layer, particularly to a semiconductor device having an SOI structure in which isolation of elements is realized by a trench.
2. Discussion of Background
An SOI structure is obtained by forming elements on a silicon layer formed on an insulating layer, not by forming elements on a semiconductor substrate as in conventional semiconductor devices.
FIG. 12 is a cross-sectional view for showing a conventional semiconductor device having the SOI structure. As shown an insulating layer 102 was formed on a semiconductor substrate 101; and a silicon layer 103 was formed on the insulating layer 102, whereby the SOI structure was fabricated.
A plurality of active regions were formed in the silicon layer 103, and an element isolating part was formed between the active regions. In the active regions of the silicon layer 103, source/drain areas 103a were formed by injecting impurities such as phosphorus, arsenic, and boron. Simultaneously, on the silicon layer 103 between the source/drain areas 103a, a gate electrode 108 was formed interposing a gate oxide film 107, whereby a MOS transistor was fabricated. On the other hand, between the active regions, a trench 104 was formed; and an insulator 105 was embedded in an inside of the trench 104, whereby an element isolating area was fabricated.
On an SOI substrate in which MOS transistors were formed, an inter-layer insulating film was formed; a conductive wire 110 was formed on the inter-layer insulating film 109; and contact holes, in which a conductive material was embedded to electrically connect the wire 110 to the source/drain area 103a in the silicon layer 103, was formed in the inter-layer insulating film 109.
In the conventional semiconductor device having the above-mentioned SOI structure, a technique that a space 106 was formed above an interface, between the silicon 103 in a trench 104 and an insulating layer 102, positioned in a central portion of the trench 104, and stress caused in the trench 104 was absorbed and relaxed by the space 106 in order to deal with such stress caused in accordance with a volume change of the insulator, which was an element isolating area, was disclosed in JP-A-6-349940.
As a method of forming a silicon layer on an insulating layer, there were proposed a recrystallizing method for depositing an amorphous thin film or a polycrystalline thin film on an insulating layer and succeedingly recrystallizing this, an epitaxial method for depositing a crystalline thin film first on the insulating layer, an insulating layer embedding method of preparing a single crystal wafer and embedding the insulating layer thereinto, and a bonding method of bonding a single crystal wafer to an insulator.
Among these method, the recrystallizing method and the epitaxial method did not cause oxidation of the insulating layer at a time of forming the silicon layer on the insulating layer. On the other hand, the insulating layer embedding method and the bonding method were to form the insulating layer by oxidizing a silicon layer because, in the insulating layer embedding method, the insulating layer was formed by implanting oxygen and nitrogen into a single crystal wafer and oxidizing this, and, in the bonding method, the insulating layer was formed by thermal oxidation on the single crystal wafer and bonding to other wafers. In such an SOI substrate formed along with oxidation of the silicon layer, fixed positive charges were generated in a region which is in the insulating layer of the SOI substrate and within about 200 xc3x85 from an interface between the insulating layer and the silicon layer, during a process of oxidation. Therefore, when the SOI substrate of the conventional semiconductor device was formed by the insulating layer embedding method or the bonding method, there was a possibility that the SOI substrate was affected by the fixed charges existing in the insulating layer. Particularly, when an n-type MOS transistor was formed, a parasitic MOS was apt to be generated in a silicon layer in the vicinity of a gate electrode by an effect of the positive fixed charges.
The parasitic MOS cause the following disadvantages. FIG. 14a and 14b respectively are schematical plan and cross sectional views for illustrating the parasitic MOS produced in a transistor. Numerical reference 200 designates a parasitic MOS; numerical reference 201 designates a gate of transistor; numerical reference 202 designates a transistor; and numerical reference 203 designates an SOI layer.
Such a parasitic MOS 200 is produced on an end of a device such as the transistor 202 illustrated in FIGS. 14a and 14b. When a threshold voltage Vth of the parasitic MOS became lower than that of the transistor, there was a problem that a leakage current was increased. FIG. 15 illustrates properties of a drain current Idxe2x80x94a gate voltage Vg both in a case that Vth of the parasitic MOS is decreased and a case that this Vth is ideal, in which numerical reference 210 designates the case that Vth of the parasitic MOS is increased, and numerical reference 211 designates the case that Vth is ideal.
In the case 210, when Vg=0V, Id is increased to cause the increment of the leakage current in comparison with the case 211.
Incidentally, the SOI substrate was formed by methods other than the insulating layer embedding method and the bonding method, the above-mentioned fixed charges were not generally generated. However, in a case that the device was used under circumstances, which were exposed to many radiations as in a nuclear electric power station and an artificial satellite, radiations entered into the insulating layer and therefore pairs of an electron and a hole were generated in the insulating layer. Thus, an effect similar to that by the positive charges was generated by these holes.
It is an object of the present invention to solve the above-mentioned problems inherent in the conventional technique and to provide a semiconductor device, in which fixed charges or holes existing on a side of the insulating layer of an interface between a silicon layer and the insulating layer are decreased.
Another object of the present invention is to provide a semiconductor device, in which parasitic MOS in a silicon layer in the vicinity of gate electrodes can be prevented from generating.
According to the first aspect of the present invention, there is provided a semiconductor device comprising an SOI substrate in which a silicon layer is formed on an insulating layer, a plurality of active regions disposed in the silicon layer to be horizontally arranged, and an element isolating part of trench-like shape made of an insulator embedded between the active regions in the silicon layer, wherein the insulating layer includes spaces positioned in the vicinity of interfaces between the active regions and the element isolating part.
According to the second aspect of the present invention, there is provided the semiconductor device in which the element isolating parts are embedded to reach an inside of the insulating layer of the SOI substrate.
According to the third aspect of the present invention, there is provided the semiconductor device in which an insulating layer embedding method or a bonding method is used to form the SOI substrate to enable fixed charges generated in the insulating layer to decrease by forming the spaces even not under special conditions, wherein a mechanism of decreasing the fixed charges is to relax a stress caused at an interface between SiO2 and Si by a difference of their coefficients of thermal expansion and a thermal budget in a process of semiconductor wafer, the stress cuts dangling bonds between SiO2 and Si to resultantly generate the fixed charges.
According to the forth aspect of the present invention, there is provided a semiconductor device comprising an SOI substrate in which a silicon layer is formed on an insulating layer, a plurality of active regions formed in the silicon layer to be horizontally arranged, and element isolating parts having trench-like shape made of insulators embedded between the active regions in the silicon layer, wherein the active regions include an MOS transistor composed of source/drain areas arranged opposite each other with respect to the element isolating parts in the silicon layer and a gate electrode arranged on the silicon layer between the source/drain areas; and the insulating layer includes spaces positioned in the vicinity of interfaces between the active regions and the element isolating parts.
According to the fifth aspect of the present invention, there is provided the semiconductor device in which the gate electrodes extend on the interfaces between the active regions and the element isolating parts.
According to the sixth aspect of the present invention, there is provided the semiconductor device in which the MOS transistors is n-type and the spaces are positioned in the vicinity of the interfaces in consideration of generation of a parasitic metal oxide semiconductor in the vicinity of channels of the MOS transistors.